Marco Mestice
Marco Mestice received the M.Sc. and Ph.D. degrees (cum Laude) in electronic engineering and Smart Industry, respectively, from the University of Pisa, Italy, in 2020 and 2024. From June 2020 to October 2020, he was a Pre-Doctoral researcher with the Department of Information Engineering (DII), University of Pisa, while since January 2024 he is a researcher at DII.
Phase-Locked Loop, Frequency-Locked Loop, Harsh Environments, High-temperature, Radiation, Charge Pump PLL, Bang-Bang PLL, Integrated Circuits.
His research is focused on reliable high-speed integrated circuits for communication applications in harsh environments, and for high-performance computing applications. His main research interests include the development and design of Phase- and Frequency-Locked Loops for high-temperature and radiation-pervaded environments, and for LPDDR4x memory interface and Power Management Systems.
From 2019 to 2023 he was associated with the National Institute of Nuclear Physics, Pisa Section. Since 2022 he is involved in The European Pilot using Independent Local & Open Technology (The EUPILOT) and European Processor Initiative (EPI) European projects. Since January 2024 he collaborates with STMicroelectronics. In March 2023 he joined the “28 nm Mixed-Signal Workshop” hosted by CERN. In June 2023 he was a visiting PhD Student at Rheinland-Pfälzische Technische Universität Kaiserslautern-Landau (RPTU), Germany. From September 2023 to November 2023 he was a visiting PhD student at Eidgenössische Technische Hochschule Zürich (ETHZ), Switzerland.